The present invention relates to an operational amplifier circuit, and, more particularly, to a rail-to-rail type operational amplifier circuit, a push-pull type operational amplifier circuit, a current output circuit and an analog switch circuit, which are used as a basic operational circuit in an electronic device.
FIG. 1 is a schematic circuit diagram of a rail-to-rail type operational amplifier circuit 10 according to first prior art.
A first input voltage VINxe2x88x92 is applied to the inverting input terminal (negative input terminal) 11 of the operational amplifier circuit 10, and a second input voltage VIN+ is applied to the non-inverting input terminal (positive input terminal) 12 thereof. The input terminals 11 and 12 are respectively connected to the gates of P channel MOS transistors (hereinafter referred to as xe2x80x9cPMOS transistorsxe2x80x9d) Q1 and Q2, which constitute a first differential pair 13. The sources of the transistors Q1 and Q2 are connected together and a node between the sources is connected to a high-potential power supply VD via a first current source 14, which supplies a bias current to the transistors Q1 and Q2. The input terminals 11 and 12 are also respectively connected to the gates of N channel MOS transistors (hereinafter referred to as xe2x80x9cNMOS transistorsxe2x80x9d) Q3 and Q4, which constitute a second differential pair 15. The sources of the transistors Q3 and Q4 are connected together, and a node between the sources is connected to a low-potential power supply GND via a second current source 16, which supplies a bias current to the transistors Q3 and Q4.
The drains of the transistors Q1 and Q2 are connected to the low-potential power supply GND via a pair of NMOS transistors Q5 and Q6, which constitute a first current mirror circuit 17. The gates of the transistors Q5 and Q6 are connected together and a node between the gates is connected to the drain of the transistor Q5.
The drain of the transistor Q6 is connected to the gate of an output NMOS transistor Q7. The source of the transistor Q7 is connected to the low-potential power supply GND and the drain is connected to the high-potential power supply VD via a resistor R1. The drain of the transistor Q7 is connected to an output terminal 18.
The drains of the transistors Q3 and Q4 are respectively connected to second and third current mirror circuits 19 and 20. The second current mirror circuit 19 includes a pair of PMOS transistors Q8 and Q9. The drain of the transistor Q3 is connected to the high-potential power supply VD via the transistor Q8. The source of the transistor Q9 is connected to the high-potential power supply VD and the drain of the transistor Q9 is connected to the drain of the transistor Q6.
The third current mirror circuit 20 includes a pair of PMOS transistors Q10 and Q11. The drain of the transistor Q4 is connected to the gates of the transistors Q8 and Q9 via the transistor Q10. The source of the transistor Q11 is connected to the high-potential power supply VD, and the drain of the transistor Q11 is connected to the drain of the transistor Q5.
The first and second current sources 14 and 16, which are controlled by an unillustrated control circuit, supply bias currents I1 and I2 according to the input voltages VIN+ and VINxe2x88x92 as shown in FIG. 2. Specifically, when the first and second input voltages VINxe2x88x92 and VIN+ are low, the first differential pair 13 drives the transistors Q5 and Q6, and when the input voltages VIN+ and VINxe2x88x92 are high, the second differential pair 15 drives the transistors Q5 and Q6.
As the first and second differential pairs 13 and 15 operate this way, the sum of the bias currents I1 and I2 of the first and second current sources 14 and 16 is constant. Even when the potential difference between the input voltages VIN+ and VINxe2x88x92 is zero, therefore, constant currents I5 and I6 flow in the transistors Q5 and Q6, respectively.
The currents flowing the transistors Q1 and Q2 of the first differential pair 13 are directly supplied to the transistors Q5 and Q6, and the currents flowing the transistors Q3 and Q4 of the second differential pair 15 are supplied to the transistors Q5 and Q6 via the second and third current mirror circuits 19 and 20. Accordingly, the current supplies to the transistors Q5 and Q6 from the second differential pair 13 are delayed by the operational times of the second and third current mirror circuits 19 and 20, so that the currents flowing the transistors Q5 and Q6 transiently vary.
When the potential difference between the input voltages VIN+ and VINxe2x88x92 is maintained at zero and the absolute value of the input voltage changes, therefore, the currents I5 and I6 transiently vary every time the enabling/disabling of the first and second current sources 14 and 16 is switched. This decreases the common mode rejection ratio (CMRR) of the operational amplifier circuit 10.
When both the first and second current sources 14 and 16 are used and the transistors Q1-Q4 of the first and second differential pairs 13 and 15 are operating, the output transistor control by the first current source 14 and the output transistor control by the second current source 16 are executed simultaneously. In this case, there is a time lag between the output transistor control by the second current source 16 and the output transistor control by the first current source 14. This reduces the frequency characteristic of the operational amplifier circuit 10.
Further, the voltages on which the PMOS transistors Q1 and Q2 and the NMOS transistors Q3 and Q4 operate vary according to the process conditions. Depending on process variation, therefore, the first or second differential pair 13 or 15 may not operate.
Suppose that the operational points of the PMOS transistors Q1 and Q2 and the NMOS transistors Q3 and Q4 lie between a reference voltage Va and the high-potential power supply VD due to a process variation as shown in FIG. 2. Then, the NMOS transistors Q3 and Q4 do not operate even when the first and second input voltages VINxe2x88x92 and VIN+, which change the first and second bias currents I1 and I2, are supplied.
Therefore, the NMOS transistors Q3 and Q4 do not operate even if the first and second input voltages VINxe2x88x92 and VIN+ rise, and the PMOS transistors Q1 and Q2 of the first differential pair 13 stop operating when the first and second bias currents I1 and I2 are switched from one to the other.
FIG. 3 is a circuit diagram of a push-pull type operational amplifier circuit 300 according to second prior art circuit.
The operational amplifier circuit 300 has a constant current source 11b which supplies a constant current Ia to a current mirror circuit 12b. The current mirror circuit 12b includes NMOS transistors Q1b, Q2b and Q3b. The constant current Ia is supplied to the drain of the transistor Q1b. The drain of the transistor Q1b is connected to the gates of the transistors Q1b, Q2b and Q3b, the sources of which are connected to a low-potential power supply VS. The drain of the transistor Q2b is connected to a current mirror circuit 13b, and the drain of the transistor Q3b is connected to a differential input circuit 14b. 
The transistor Q2b has the same size as the transistor Q1b and supplies the current mirror circuit 13b with a drain current that is substantially the same as the constant current Ia of the constant current source 11b. The transistor Q3b is double the size of the transistor Q1b and supplies the differential input circuit 14b with a drain current that is double the constant current Ia of the constant current source 11b. 
The current mirror circuit 13b includes PMOS transistors Q4b and Q5b. The drain of the transistor Q4b is connected to the drain of the transistor Q2b. The sources of the transistors Q4b and Q5b are connected to a high-potential power supply VD, and the gates of the transistors Q4b and Q5b are connected together to the drain of the transistor Q4b. 
The transistor Q5b has double the size of the transistor Q4b and produces a drain current that is twice as large as the current flowing the transistor Q5b. As the drain current, which is substantially the same as the constant current Ia, flows in the transistor Q4b, a current that is double the constant current Ia is output from the drain of the transistor Q5b. 
The differential input circuit 14b includes a pair of NMOS transistors Q6b and Q7b and a pair of PMOS transistors Q8b and Q9b. The sources of the transistors Q6b and Q7b are connected to the drain of the transistor Q3b. The drain of the transistor Q6b is connected to the drain of the transistor Q8b and the gates of the transistors Q8b and Q9b. The source of the transistor Q8b is connected to the high-potential power supply VD. The drain of the transistor Q7b is connected to the drain of the transistor Q9b, the source of which is connected to the high-potential power supply VD.
The differential input circuit 14b receives a bias current from the transistor Q3b and sets a potential at a node N1b between the transistors Q7b and Q9b in accordance with the potential difference between the voltages of input signals IM and IP, which are applied to the gates of the transistors Q6b and Q7b. 
The node N1b is connected to the gate of a PMOS transistor Q10b and the gate of a PMOS transistor Q11b at the final output stage. The sources of the transistors Q10b and Q11b are connected to the high-potential power supply VD. The drain of the transistor Q11b is connected to an output terminal To. The transistor Q11b is ten times the size of the transistor Q10b and produces a drain current that is ten times the drain current of the transistor Q10b. 
The drain of the transistor Q10b is connected to a current mirror circuit 15b. The current mirror circuit 15b includes NMOS transistors Q12b and Q13b. The drain of the transistor Q12b is connected to the drain of the transistor Q10b. The sources of the transistors Q12b and Q13b are connected to the low-potential power supply VS, and the drain of the transistor Q12b is connected to the gates of the transistors Q12b and Q13b. 
The transistor Q13b has substantially the same size as the transistor Q12b and produces the drain current of the transistor Q12b (i.e., the drain current of the transistor Q12b is substantially the same as the drain current of the transistor Q10b).
The drain of the transistor Q13b is connected to the drain of the transistor Q5b, and a node N2b between the transistors Q13b and Q5b is connected to a current mirror circuit 16b. 
The current mirror circuit 16b includes NMOS transistors Q14b and Q15b. The drain of the transistor Q14b is connected to the node N2b. The sources of the transistors Q14b and Q15b are connected to the low-potential power supply VS and the drain of the transistor Q14b is connected to the gates of the transistors Q14b and Q15b. 
The transistor Q15b is located at the last output stage, and its drain is connected to the output terminal To. The transistor Q14b is substantially the same size as each of the transistors Q12b, Q13b, Q1b and Q2b. The transistor Q15b is ten times the size of the transistor Q14b and produces a drain current that is ten times the current flowing the transistor Q14b. 
The operational amplifier circuit 300 performs a push-pull operation as the gate voltages of the PMOS transistor Q11b and NMOS transistor Q15b are controlled such that the ON/OFF state of the transistor Q11b is always opposite the ON/OFF state of the transistor Q15b. 
When the voltage of the input signal IP is higher than the voltage of the input signal IM, a gate voltage Vg(Q11b) at the node N1b or of the transistor Q11b is given by:
Vg(Q11b)=VS+V(Q3b)+V(Q7b)
where V(Q3b) is the saturation voltage (source-drain voltage) of the transistor Q3b and V(Q7b) is the saturation voltage of the transistor Q7b. 
At this time, all the constant current of the transistor Q5b flows in the transistor Q13b because of the transistor Q10b, which operates in a common mode with the output-stage transistor Q11b, and the gate voltage of the transistor Q15b is set while pulling a current ten times the constant current from the drain of the transistor Q15b. 
When the voltage of the input signal IP is lower than the voltage of the input signal IM, the gate voltage Vg(Q11b) of the transistor Q11b rises to a level given below.
Vg(Q11b)=VDxe2x88x92V(Q9b)
where V(Q9b) is the saturation voltage of the transistor Q9b. 
At this time, all the constant current of the transistor Q5b flows in the transistor Q14b because of the transistor Q10b, which operates in a common mode with the output-stage transistor Q11b, so that the gate voltage of the transistor Q15b becomes equal to the voltage of the low-potential power supply VS.
As apparent from the above, the operational amplifier circuit 300 generates an operational amplifier output by applying voltages that lie substantially in the supply voltage range to the gates of the transistors Q11b and Q15b in an opposite phase manner.
The operational amplifier circuit 300 requires that when the voltages of the input signals IP and IM are substantially the same, the drain currents of the transistors Q11b and Q15b should be substantially identical.
When IP=IM, the currents flowing the transistors Q8b and Q9b are substantially identical. Therefore, the drain current of the transistor Q11b is determined by the ratio of the size of the transistor Q11b to the sizes of the transistors Q8b and Q9b. The drain current of the transistor Q15b is determined by the drain current of the transistor Q10b and the ratio of the size of the current mirror circuit 15b to the size of the current mirror circuit 16b. 
As apparent from the above, a voltage that lies substantially in the supply voltage range is applied to the gate of the transistor Q11b, and the full current driving performance of the transistor is demonstrated. The full current driving performance of the transistor Q7b is demonstrated by adjusting the size of the transistor Q15b such that when the voltages of the input signals IP and IM are substantially identical, the current flowing the transistor Q13b becomes larger and the current flowing the transistor Q14b becomes smaller.
However, only the last stage transistor Q11b performs voltage-current conversion as seen from the transistors Q8b and Q9b in the push operation of the operational amplifier circuit 300, while the operations of the transistors Q10b and Q13b and the last stage transistor Q15b are needed in the pull operation. This makes the operational speed of the operational amplifier circuit 300 of the second prior art relatively slow.
FIG. 4 is a schematic circuit diagram of an operational amplifier circuit 400 according to third prior art circuit which is preferred for fast operation. In the operational amplifier circuit 400, a transistor Q15b at the last output stage is driven by the drain voltage of a transistor Q8b, which shows a voltage change opposite to a voltage change at a node N1b. 
A node N3b between the transistors Q8b and Q6b is connected to the gate of a PMOS transistor Q10b. The gate of the transistor Q15b at the last output stage is connected to the gate of an NMOS transistor Q12b to which the drain current of the transistor Q10b is supplied. The operational amplifier circuit 400 does not have the NMOS transistors Q13b and Q14b and the transistors Q2b, Q4b and Q5b shown in FIG. 3.
In the operational amplifier circuit 400, the transistors Q12b and Q15b perform voltage-current conversion as seen from the transistors Q8b and Q9b. Therefore, the operational amplifier circuit 400 operates faster than the operational amplifier circuit 300 of FIG. 3.
The transistor Q10b is connected to the drain and gate of the transistor Q8b and forms a current mirror circuit together with the transistor Q8b. When the voltages of the input signals IP and IM are not identical, therefore, only the current that is the twice as large as the current that flows when the voltages of the input signals IP and IM are identical flows in the transistor Q15b. While the operational amplifier circuit 400 operates fast, therefore, the output driving performance falls.
FIG. 5 is a schematic circuit diagram of a current output circuit 500 according to fourth prior art circuit.
The current output circuit 500 includes a current mirror circuit 11c and a current source 12c. The current mirror circuit 11c includes PMOS transistors Q11c and Q12c. The sources of the transistors Q11c and Q12c are connected to a high-potential power supply VD and the drain of the transistor Q11c is connected to the gates of the transistors Q11c and Q12c. 
The drain of the transistor Q11c is connected to the current source 12c, and the drain of the transistor Q12c is connected to an output terminal OUT. As a predetermined voltage is applied to the output terminal, a current I12c, which is substantially the same as the drain current of the transistor Q11c (i.e., the current I11c of the current source 12c), flows in the transistor Q12c. That is, the current output circuit 500 outputs the current I12c, which is substantially the same as the input current I11c. 
The current output circuit 500 is used in an analog circuit. Depending on the structure of the analog circuit, PMOS transistors are replaced with NMOS transistors.
FIG. 6 is a schematic circuit diagram of an analog switch circuit 600 according to fifth prior art circuit.
The analog switch circuit 600 includes a current source 21c, a current mirror circuit 22c, a differential pair 23c and a current mirror circuit 24c. 
The current source 21c supplies a current I21c to the current mirror circuit 22c. The current mirror circuit 22c includes NMOS transistors Q21c and Q22c. The drain of the transistor Q21c is connected to the current source 21c. The sources of the transistors Q21c and Q22c are connected to a low-potential power supply VS and the drain of the transistor Q21c is connected to the gates of the transistors Q21c and Q22c. The transistor Q22c is double the size of the transistor Q21c and its drain is connected to the differential pair 23c. The transistor Q22c supplies the differential pair 23c with a bias current I22c that is double the drain current of the transistor Q21c (i.e., the current I21c of the current source 21c).
The differential pair 23c includes NMOS transistors Q23c and Q24c. A node between the sources of the transistors Q23c and Q24c is connected to the drain of the transistor Q22c. The drains of the transistors Q23c and Q24c are respectively connected to the drains of PMOS transistors Q25c and Q26c of the current mirror circuit 24c. The sources of the transistors Q25c and Q26c are connected to a high-potential power supply VD, and the drain of the transistor Q25c is connected to the gates of the transistors Q25c and Q26c. The gate of the transistor Q23c is connected to an input terminal Ti to which an input signal VIN is supplied. The gate of the transistor Q24c is connected to an output terminal To and the drain of the transistor Q24c. An output signal VOUT is output from the output terminal To.
The analog switch circuit 600 transfers only the voltage component to the output terminal To from the input terminal Ti. In other words, the analog switch circuit 600 does not transfer the current component. When drain currents I23c and I24c of the transistors Q23c and Q24c become substantially equal to each other, the source-gate voltages Vgs of the transistors Q23c and Q24c becomesubstantially equal to each other. When the same drain current is supplied from the transistors Q25c and Q26c, therefore, the output signal VOUT, the voltage of which is substantially equal to the voltage of the input signal VIN, is output from the output terminal To.
MOS transistors have capacitors with respect to the individual terminals and individual node voltages are determined by charge and discharge of the capacitors. In the current output circuit 500, for example, as the capacitor of the transistor Q11c is charged and discharged by the high-potential power supply VD and the current source 12, the gate voltage of the transistor Q12c is determined. The charge/discharge time is determined by a capacitor and the time constant of resistor and current. The greater the sizes of the transistors Q11c and Q12c become or the smaller the current that flows becomes, the longer the charge/discharge time becomes.
The operational speed of the analog switch circuit 600 of FIG. 6 is determined by the operational speeds of the differential pair 23c and the current mirror circuit 24c. The operational speed of the operational amplifier circuit 400 of FIG. 4 is determined by the differential input circuit 14b, the transistors Q10b and Q11b and the current mirror circuit that includes the transistors Q12b and Q15b. 
In short, the operational speeds of the current output circuit 500, the analog switch circuit 600 and the operational amplifier circuit 400 are affected by the operational speed of the current mirror circuit. That is, the operational time of the current mirror circuit prevents the operational speed of the entire circuit from being improved.
Accordingly, it is a first object of the present invention to provide a rail-to-rail type operational amplifier circuit that has an improved common mode rejection ratio and improved frequency characteristic.
It is a second object of the present invention to provide an operational amplifier circuit that operates at a high speed and has an improved output driving performance.
It is a third object of the present invention to provide a current output circuit, analog switch circuit and operational amplifier circuit that operate at a high speed.
In a first aspect of the present invention, an operational amplifier circuit is provided that includes a first differential pair, which includes a first transistor responsive to a first input voltage and a second transistor responsive to a second input voltage, and a second differential pair, which includes a third transistor responsive to the first input voltage and a fourth transistor responsive to the second input voltage. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source, which is connected to the first differential pair, supplies a first bias current to the first differential pair. A second current source, which is connected to the second differential pair, supplies a second bias current to the second differential pair. A third current source, which is connected to the fifth transistor, supplies a third bias current to the fifth transistor. A fourth current source, which is connected to the sixth transistor, supplies a fourth bias current to the sixth transistor. A control circuit, which is connected to the first to fourth current sources, receives the first and second input voltages and controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.
In a second aspect of the present invention, an operational amplifier circuit is provided that includes a first differential pair, which includes a first transistor responsive to a first input voltage and a second transistor responsive to a second input voltage, and a second differential pair, which includes a third transistor responsive to the first input voltage and a fourth transistor responsive to the second input voltage. A first resistor element is connected to the first and third transistors. A second resistor element is connected to the second and fourth transistors. A first current source, which is connected to the first differential pair, supplies a first bias current to the first differential pair. A second current source, which is connected to the second differential pair, supplies a second bias current to the second differential pair. A third current source, which is connected to the first resistor element, supplies a third bias current to the first resistor element. A fourth current source, which is connected to the second resistor element, supplies a fourth bias current to the second resistor element. A control circuit, which is connected to the first to fourth current sources, receives the first and second input voltages and controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.
In a third aspect of the present invention, a method of controlling first and second bias currents respectively supplied to first and second differential pairs of an operational amplifier circuit is provided. The second bias current is controlled in accordance with one of first and second input voltages. The first bias current is controlled using a predetermined constant current and a current substantially equal to the second bias current.
In a fourth aspect of the present invention, an operational amplifier circuit is provided that includes a first differential pair, which receives a first bias current and operating in response to first and second input voltages, and a second differential pair, which receives a second bias current and operating in response to the first and second input voltages. A first current source is connected to the first differential pair. A second current source, which is connected to the second differential pair, produces the second bias current. A control circuit, which is connected to the first and second current sources, controls the first current source such that the first current source produces a constant current. The control circuit produces the first bias current at a node between the first differential pair and the first current source by adding a current that is substantially equal to the second bias current to the constant current in accordance with one of the first and second input voltages.
In a fifth aspect of the present invention, an operational amplifier circuit is provided that includes a first differential pair including a first P channel transistor responsive to a first input voltage and a second P channel transistor responsive to a second input voltage. The first differential pair receives a first bias current. A second differential pair includes a first N channel transistor responsive to the first input voltage and a second N channel transistor responsive to the second input voltage. The second differential pair receives a second bias current. A first current source includes a third P channel transistor connected between the first differential pair and a high-potential power supply. A second current source, which includes a third N channel transistor connected between the second differential pair and a low-potential power supply, produces the second bias current. A control circuit controls the first current source such that the first current source produces a predetermined constant current and controls the first and second bias currents. The control circuit includes a third current source, which is connected to the second current source. The third current source includes a fourth N channel transistor that produces a current substantially equal to the second bias current. The control circuit includes a fifth N channel transistor connected to the fourth N channel transistor and a node between the first current source and the first differential pair. The fifth N channel transistor is responsive to one of the first and second input voltages.
In a sixth aspect of the present invention, an operational amplifier circuit is provided that includes a first differential pair including a first P channel transistor responsive to a first input voltage and a second P channel transistor responsive to a second input voltage. The first differential pair receives a first bias current. A second differential pair includes a first N channel transistor responsive to the first input voltage and a second N channel transistor responsive to the second input voltage. The second differential pair receives a second bias current. A first current source includes a third P channel transistor connected between the first differential pair and a high-potential power supply. A second current source, which includes a third N channel transistor connected between the second differential pair and a low-potential power supply, produces the second bias current. A control circuit controls the second current source such that the second current source produces a predetermined constant current and controls the first and second bias currents. The control circuit includes a third current source connected to the first current source. The third current source includes a fourth P channel transistor that produces a current substantially equal to the first bias current. The control circuit includes a fifth P channel transistor connected to the fourth P channel transistor and a node between the second current source and the second differential pair. The fifth P channel transistor is responsive to one of the first and second input voltages.
In a seventh aspect of the present invention, a control circuit, which is connected to a first power supply, is provided. The control circuit controls a first output current flowing in a first current source including a first transistor cascade-connected to a second transistor that has the same polarity as that of the first transistor. The control circuit includes a second current source connected to the first power supply. The second current source includes a third transistor, a second output current that is substantially equal to the first output current flows to the second current source. A fourth transistor is cascade-connected to the third transistor. The fourth transistor has the same polarity as that of the third transistor, and the second and fourth transistors control the first and second output currents by controlling saturation/non-saturation of the first and third transistors in accordance with a voltage signal. A third current source, which is connected to the second power supply, produces a third output current. A fourth output current, the phase of which is opposite to that of the first output current, is produced by adding the second output current and the third output current.
In an eighth aspect of the present invention, a current output circuit is provided that includes a constant current source circuit that includes a first transistor and a first resistor element connected between the gate and the source of the first transistor. The constant current source circuit makes a first current flowing across the first resistor element equal to a first drain current flowing in the first transistor. An output stage circuit includes a second transistor and a second resistor element connected between the gate and the source of the second transistor. The resistance of the second resistor element is proportional to the resistance of the first resistor element. The output stage circuit produces a second current from the first current in accordance with a current ratio expressed by a reciprocal of a ratio of the resistance of the first resistor element to the resistance of the second resistor element and sets a gate voltage of the second transistor by supplying the second current to the second resistor element.
In a ninth aspect of the present invention, a current output circuit is provided that includes a first transistor, the drain of which receives a first current, a first resistor element connected between the gate and the source of the first transistor. The gate of a second transistor is connected to the drain of the first transistor and the source thereof is connected to the gate of the first transistor. A drain current is generated at the drain of the second transistor. The resistance of a second resistor element is related to the resistance of the first resistor element. The size of a third transistor is related to the size of the first transistor. The second resistor element is connected between the gate and the source of the third transistor. A second current originating from the drain current of the second transistor is supplied to the gate of the third transistor. A third current, which is related to the first current, is produced at the drain of the third transistor.
In a tenth aspect of the present invention, an analog switch circuit is provided that includes a first transistor, the drain of which receives a first current, a first resistor element connected between the gate and the source of the first transistor, and a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor. A drain current is generated at the drain of the second transistor. A differential pair includes an input transistor, the source of which receives a second current originating from the drain current of the second transistor and the gate of which receives an input signal. The differential pair includes an output transistor, the source of which receives the second current, the gate of which is connected to an output terminal of the analog switch circuit, and the drain of which is connected to the gate of the output transistor. A second resistor element is connected to the drain of the input transistor. The resistance of the second resistor element is related to the resistance of the first resistor element. The size of a third transistor is related to the size of the first transistor. The second resistor element is connected between the gate and the source of the third transistor, the drain of the third transistor is connected to the drain of the output transistor. A third current, which is related to the first current, is generated at the drain of the third transistor.
In an eleventh aspect of the present invention, an operational amplifier circuit is provided that includes a first transistor the drain of which receives a first current, a first resistor element connected between the gate and the source of the first transistor, and a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor. A differential pair includes first and second differential transistors, the sources of which receive a second current originating from the drain current of the second transistor and the gates of which respectively receive first and second input signals. Second and third resistor elements are respectively connected to the drains of the first and second differential transistors. A third transistor has the gate which is connected to a first node between a first terminal of the second resistor element and the drain of the first differential transistor. The source of the third transistor is connected to a second terminal of the second resistor element. A third current, which is related to the first current, is generated at the drain of the third transistor. A first output transistor has the gate which is connected to a second node between a third terminal of the third resistor element and the drain of the second differential transistor. The source of the first output transistor is connected to a fourth terminal of the third resistor element. A fourth current, which is related to the first current, is generated at the drain of the first output transistor. A fourth resistor element is connected to the drain of the third transistor. A second output transistor has the gate which is connected to a third node between the drain of the third transistor and the fourth resistor element. The source of the second output transistor is connected to the fourth resistor element. A fifth current, which corresponds to a gate voltage of the third transistor, is generated at the drain of the second output transistor based on the third current.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.